1. Field of the Invention
The present invention relates to structures of a memory cell and a peripheral circuit of a DRAM (Dynamic Random Access Memory) of a semiconductor device, and a method for manufacturing the structures.
2. Description of the Background Art
FIG. 15 is a view showing a sectional structure of a semiconductor device according to the prior art. FIG. 15 shows a technique which has been disclosed in Japanese Patent Laying Open Gazette No. 7-153966.
In FIG. 15, the reference numeral 101 denotes a substrate for producing a SOI (Silicon On Insulator) structure, the reference numeral 102 denotes an insulation film provided on the substrate 101, the reference numeral 103 denotes a silicon layer provided on the insulation film 102, the reference numeral 104 denotes an isolation film which is an insulation film formed in a passivation region on the insulation film 102, the reference numeral 105 denotes a gate insulation film provided on a surface of a region corresponding to a channel region of a TFT (thin film transistor) which is built in the silicon layer 103, the reference numeral 106 denotes a gate electrode of the TFT which is formed on the gate insulation film 105, and the reference numerals 107a and 107b denote source/drain regions of the TFT which are built in the silicon layer 103 with the channel region of the TFT interposed therebetween. The reference numeral 108 denotes an insulation film for insulating the gate electrode 106 from a conductive member provided thereon.
Furthermore, a trench 109 is formed in contact with the source/drain region 107a by etching from a surface of the silicon layer 103 to a portion of the substrate 101 which has a predetermined depth. A storage node 110 constituting a trench capacitor is formed in tight contact with an internal wall of the trench 109. An upper end of the storage node 110 and an end of the source/drain region 107a come in contact with each other and are electrically connected to each other. Furthermore, a capacitor insulation film 111 is formed on a surface of the storage node 110, and a cell plate 112 is buried in a surface of the capacitor insulation film 111 with the trench 109 completely filled up. The reference numeral 113 denotes a polypad provided for electrically connecting a bit line 114 provided above the TFT to the source/drain region 107b.
In a memory cell region of the semiconductor device shown in FIG. 15, the trench capacitor is formed adjacently to the TFT, and the storage node 110 constituting the trench capacitor is formed on a surface of the internal wall of the trench 109 and is provided in contact with the source/drain region 107a of the TFT which is built in the silicon layer 103 formed on the substrate 101 with the insulation film 102 provided therebetween. As seen on a plane, the trench capacitor and the TFT are provided adjacently but are not superposed each other. FIG. 16 shows a structure of a peripheral circuit of the semiconductor device according to the prior art.
In a sectional structure illustrated in FIG. 16, a MOS transistor has a source/drain region formed on a substrate (semiconductor substrate) 101 (The MOS transistor will be hereinafter referred to as a bulk transistor 115. The transistor comprises two source/drain regions interposing a channel region therebetween, and a gate electrode formed on the channel region with a gate insulation film provided therebetween.) Only a bit line 114 or an aluminum wiring 116 is provided above the MOS transistor and elements are thinly arranged two-dimensionally in a horizontal direction. The elements are not superposed each other three-dimensionally. As shown in the sectional structure, in the case where five bulk transistors 115 are arranged on the substrate 101, a space of 8.9 .mu.m is required on the condition that a gate length of each transistor to be formed is 0.35 .mu.m.
In the structure of the peripheral circuit of the semiconductor device according to the prior art, elements are not provided on an isolation film (a trench isolation, in this case) 104a. An element such as a transistor is formed in a region other than the isolation region 104a, thus constituting the peripheral circuit.
In FIG. 16, the reference numeral 114a denotes a bit line contact and the reference numeral 116a denotes an Al wiring contact.